LH28F008SAT-85 Sharp Microelectronics, LH28F008SAT-85 Datasheet - Page 20

• Manufacturer Part Number: LH28F008SAT-85
• Description: IC FLASH 8MBIT 85NS 40TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F008SAT-85

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1836; LHF08S49

sharp
V
Status Registers
Byte write and block erase completion are not guaranteed if
V
Register (SR.3) is set to "1", a Clear Status Register com-
mand MUST be issued before further byte write/block erase
attempts are allowed by the WSM. Otherwise, the Byte
Write (SR.4) or Erase (SR.5) Status bits of the Status Reg-
ister will be set to "1"s if error is detected. RP# transitions to
V
tions. Data is partially altered in either case, and the com-
mand sequence must be repeated after normal operation is
restored. Device poweroff, or RP# transitions to V
the Status Register to initial value 10000 for the upper 5
bits.
The Command User Interface latches commands as issued
by system software and is not altered by V
transitions or WSM actions. Its state upon powerup, after
exit from deep powerdown or after V
V
After byte write or block erase is complete, even after V
transitions down to V
must be reset to Read Array mode via the Read Array com-
mand if access to the memory array is desired.
Power Up/Down Protection
The LH28F008SAT-85 is designed to offer protection
against accidental block erasure or byte writing during
power transitions. Upon power-up, the LH28F008SAT-85 is
indifferent as to which power supply, V
first. Power supply sequencing is not required. Internal cir-
cuitry in the LH28F008SAT-85 ensures that the Command
User Interface is reset to the Read Array mode on power up.
PP
IL
LKO
CC
during byte write and block erase also abort the opera-
, V
drops below V
, is Read Array Mode.
PP
, RP# Transitions and the Command/
PPH
PPL
. If the V
, the Command User Interface
PP
Status bit of the Status
PP
CC
or V
transitions below
CC
, powers up
PP
IL
or CE#
, clear
LHF08S49
PP
A system designer must guard against spurious writes for
V
WE# and CE# must be low for a command write, driving
either to V
architecture provides an added level of protection since al-
teration of memory contents only occurs after successful
completion of the two-step command sequences.
Finally, the device is disabled until RP# is brought to V
regardless of the state of its control inputs. This provides an
additional level of memory protection.
Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device opera-
tion, but also for data retention during system idle time.
Flash nonvolatility increases usable battery life, because
the LH28F008SAT-85 does not consume any power to re-
tain code or data when the system is off.
In addition, the LH28F008SA’s deep powerdown mode en-
sures extremely low power dissipation even when system
power is applied. For example, portable PCs and other
power sensitive applications, using an array of
LH28F008SA’s for solid-state storage, can lower RP# to V
in standby or sleep modes, producing negligible power con-
sumption. If access to the LH28F008SAT-85 is again
needed, the part can again be read, following the t
t
to V
Read-Only and Write Operations and Figures 8 and 9 for
more information.
PHWL
CC
IH
voltages above V
. See AC Characteristics —
wakeup cycles required after RP# is first raised back
IH
will inhibit writes. The Command User Interface
LKO
when V
PP
is active. Since both
PHQV
and
IH
IL
,
17