LH28F008SAT-85 Sharp Microelectronics, LH28F008SAT-85 Datasheet - Page 14

no-image

LH28F008SAT-85

Manufacturer Part Number
LH28F008SAT-85
Description
IC FLASH 8MBIT 85NS 40TSOP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH28F008SAT-85

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
85ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
40-TSOP
Lead Free Status / RoHS Status
Contains lead / Request inventory verification
Other names
425-1836
LHF08S49

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH28F008SAT-85
Manufacturer:
SHARP
Quantity:
5 704
Part Number:
LH28F008SAT-85
Manufacturer:
SHARP
Quantity:
514
Part Number:
LH28F008SAT-85
Manufacturer:
SHARP
Quantity:
20 000
sharp
The Command User Interface itself does not occupy an ad-
dressable memory location. The interface register is a latch
used to store the command and address and data informa-
tion needed to execute the command. Erase Setup and
Erase Confirm commands require both appropriate com-
mand data and an address within the block to be erased.
The Byte Write Setup command requires both appropriate
command data and the address of the location to be written,
while the Byte Write command consists of the data to be
written and the address of the location to be written.
The Command User Interface is written by bringing WE# to
a logic-low level (V
are latched on the rising edge of WE#. Standard micropro-
cessor write timings are used.
Refer to AC Write Characteristics and the AC Waveforms
for Write Operations, Figure 9, for specific timing param-
eters.
5.
When V
the Status Register, intelligent identifiers, or array blocks
are enabled. Placing V
write and block erase operations as well.
SR. 7=WRITE STATE MACHINE STATUS (WSMS)
SR. 6=ERASE SUSPEND STATUS (ESS)
SR. 5=ERASE STATUS (ES)
SR. 4=BYTE WRITE STATUS (BWS)
SR. 3=V
SR. 2-0=RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use and should be masked
out when polling the Status Register.
COMMAND DEFINITIONS
1=Ready
0=Busy
1=Erase Suspended
0=Erase in Progress/Completed
1=Error in Block Erasure
0=Successful Block Erase
1=Error in Byte Write
0=Successful Byte Write
1=V
0=V
PPL
PP
PP
PP
STATUS (VPPS)
Low Detect; Operation Abort
OK
is applied to the V
IL
) while CE# is low. Addresses and data
WSMS
PPH
7
on V
PP
PP
ESS
pin, read operations from
enables successful byte
6
Table 4. Status Register Definitions
ES
5
BWS
LHF08S49
4
Device operations are selected by writing specific com-
mands into the Command User Interface. Table 3 defines
the LH28F008SAT-85 commands.
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the LH28F008SAT-85 defaults to Read
Array mode. This operation is also initiated by writing FFH
into the Command User Interface. Microprocessor read
cycles retrieve array data. The device remains enabled for
reads until the Command User Interface contents are al-
tered. Once the internal Write State Machine has started a
block erase or byte write operation, the device will not rec-
ognize the Read Array command, until the WSM has com-
pleted its operation. The Read Array command is functional
when V
Intelligent Identifier Command
The LH28F008SAT-85 contains an intelligent identifier op-
eration, initiated by writing 90H into the Command User In-
terface. Following the command write, a read cycle from ad-
dress 00000H retrieves the manufacturer code of 89H. A
read cycle from address 00001H returns the device code of
A2H. To terminate the operation, it is necessary to write
another valid command into the register. Like the Read Ar-
ray command, the intelligent identifier command is func-
tional when V
VPPS
NOTES:
RY/BY# or the Write State Machine Status bit must first be
checked to determine byte write or block erase completion, be-
fore the Byte Write or Erase Status bit are checked for success.
If the Byte Write AND Erase Status bits are set to "1"s during a
block erase attempt, an improper command sequence was en-
tered. Attempt the operation again.
If V
before another byte write or block erase operation is attempted.
The V
continuous indication of V
V
quences have been entered and informs the system if V
not been switched on. The V
report accurate feedback between V
PP
3
PP
level only after the byte write or block erase command se-
low status is detected, the Status Register must be cleared
PP
PP
Status bit, unlike an A/D converter, does not provide
=V
R
PPL
2
PP
=V
or V
PPL
PPH
or V
R
1
.
PP
PPH
PP
level. The WSM interrogates the
Status bit is not guaranteed to
.
R
0
PPL
and V
PPH
.
PP
has
11

Related parts for LH28F008SAT-85