LH28F008SAT-85 Sharp Microelectronics, LH28F008SAT-85 Datasheet - Page 12

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LH28F008SAT-85

Manufacturer Part Number
LH28F008SAT-85
Description
IC FLASH 8MBIT 85NS 40TSOP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH28F008SAT-85

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
85ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
40-TSOP
Lead Free Status / RoHS Status
Contains lead / Request inventory verification
Other names
425-1836
LHF08S49

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Data Protection
Depending on the application, the system designer may
choose to make the V
only when memory byte writes/block erases are required) or
hardwired to V
cannot be altered. The LH28F008SAT-85 Command User
Interface architecture provides protection from unwanted
byte write or block erase operations even when high voltage
is applied to V
whenever V
when RP# is at V
either design practice and encourages optimization of the
processor-memory interface.
The two-step byte write/block erase Command User Inter-
face write sequence provides additional software write pro-
tection.
4.
Flash memory reads, erases and writes in-system via the
local CPU. All bus cycles to or from the flash memory con-
form to standard microprocessor bus cycles.
Read
The LH28F008SAT-85 has three read modes. The memory
can be read from any of its blocks, and information can be
read from the intelligent identifier or Status Register. V
can be at either V
NOTES:
1. Refer to DC Characteristics. When V
2. X can be V
3. RY/BY# is V
4. Command writes involving block erase or byte write are only successfully executed when V
5. Refer to Table 3 for valid D
6. Don't use the timing both OE# and WE# are V
Read
Output Disable
Standby
Deep PowerDown
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
not busy, in Erase Suspend mode or deep powerdown mode.
BUS OPERATION
CC
IL
OL
or V
Mode
PP
is below the write lockout voltage V
PPH
when the Write State Machine is executing internal block erase or byte write algorithms. It is V
IL
. Additionally, all functions are disabled
PPL
IH
. The LH28F008SAT-85 accommodates
. When V
for control pins and addresses, and V
PP
or V
power supply switchable (available
PPH
I
N
during a write operation.
.
PP
=V
PPL
PP
=V
Notes
4,5,6
, memory contents
PPL
6
6
6
, memory contents can be read but not written or erased.
IL
.
Table 2. Bus Operations
RP#
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
LKO
IL
PPL
LHF08S49
, or
PP
or V
CE#
V
V
V
V
V
V
X
PPH
IH
IL
IL
IL
IL
IL
The first task is to write the appropriate read mode com-
mand to the Command User Interface (array, intelligent
identifier, or Status Register). The LH28F008SAT-85 auto-
matically resets to Read Array mode upon initial device
powerup or after exit from deep powerdown. The
LH28F008SAT-85 has four control pins, two of which must
be logically active to obtain data at the outputs. Chip Enable
(CE#) is the device selection control, and when active en-
ables the selected memory device. Output Enable (OE#) is
the data input/output (DQ
when active drives data from the selected memory onto the
I/O bus. RP# and WE# must also be at V
trates read bus cycle waveforms.
Output Disable
With OE# at a logic-high level (V
disabled. Output pins (DQ
pedance state.
Standby
CE# at a logic-high level (V
in standby mode. Standby operation disables much of the
LH28F008SA’s circuitry and substantially reduces device
power consumption. The outputs (DQ
high-impedence state independent of the status of OE#. If
the LH28F008SAT-85 is deselected during block erase or
byte write, the device will continue functioning and consum-
ing normal active power until the operation completes.
for V
OE#
V
V
V
V
V
X
X
PP
IH
IH
IL
IL
IL
. See DC Characteristics for V
(1,2)
WE#
V
V
V
V
V
X
X
IH
IH
IH
IH
IL
V
V
A
PP
X
X
X
X
X
IH
IL
0
=V
PPH
0
IH
0
-DQ
V
) places the LH28F008SAT-85
.
-DQ
X
X
X
X
X
X
X
PP
7
IH
) are placed in a high-im-
7
) direction control, and
), the device outputs are
PPL
0
High Z
High Z
High Z
OH
DQ
D
and V
-DQ
A2H
89H
D
OUT
when the WSM is
IN
0-7
IH
7
) are placed in a
PPH
. Figure 8 illus-
voltages.
RY/BY#
V
V
V
X
X
X
X
OH
OH
OH
(3)
9

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