LH28F008SAT-85 Sharp Microelectronics, LH28F008SAT-85 Datasheet - Page 17

• Manufacturer Part Number: LH28F008SAT-85
• Description: IC FLASH 8MBIT 85NS 40TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F008SAT-85

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1836; LHF08S49

sharp
RY/BY# and Byte Write/Block Erase Polling
RY/BY# is a full CMOS output that provides a hardware
method of detecting byte write and block erase completion.
It transitions low time t
sequence is written to the LH28F008SAT-85, and returns to
V
gorithm.
OH
FULL STATUS CHECK PROCEDURE
Status Register Data
when the WSM has finished executing the internal al-
Read (See Above)
Successful
Byte Write
SR.3=0
SR.4=0
?
?
YES
YES
Write 40H (10H),
Check if Desired
Address/Data
Byte Address
Write Byte
Full Status
Completed
Byte Write
NO
NO
Ready?
WHRL
WSM
Start
YES
after a write or erase command
NO
V
Byte Write
PP
Error
Error
Range
Figure 5. Automated Byte Write Flowchart
LHF08S49
Standby/Read
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
device to Read Array Mode
Operation
Operation
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
RY/BY# can be connected to the interrupt input of the sys-
tem CPU or controller. It is active at all times, not tristated if
the LH28F008SAT-85 CE# or OE# inputs are brought to
V
pend or deep powerdown modes.
Optional
Standby
Standby
IH
Read
Write
Write
Bus
Bus
. RY/BY# is also V
Command
Byte Write
Byte Write
Command
Setup
OH
when the device is in Erase Sus-
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR.3
1=V
Check SR.4
1=Byte Write Error
Data=40H(10H)
Address=Byte to be written
Data to be written
Address=Byte to be written
Check RY/BY#
V
Read Status Register
Check SR.7
1=Ready, 0=Busy
Toggle OE# or CE# to
update Status Register
OH
PP
=Ready, V
Low Detect
Comments
Comments
or
OL
=Busy
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