IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet

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IDT7130SA55P

Manufacturer Part Number
IDT7130SA55P
Description
IC SRAM 8KBIT 55NS 48DIP
Manufacturer
IDT, Integrated Device Technology Inc
Series
-r
Datasheets

Specifications of IDT7130SA55P

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-DIP
Density
8Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
48
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7130SA55P

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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
FEATURES
• High-speed access
• Low-power operation
• MASTER IDT7130 easily expands data bus width to
• On-chip port arbitration logic (IDT7130 Only)
• Interrupt flags for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention (LA only)
• TTL-compatible, single 5V 10% power supply
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86875
• Industrial temperature range (–40 C to +85 C) is avail-
NOTES:
1. IDT7130 (MASTER):
2. Open drain output: requires pullup
FUNCTIONAL BLOCK DIAGRAM
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP
—IDT7130/IDT7140SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT7130/IDT7140LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
16-or-more-bits using SLAVE IDT7140
BUSY
able, tested to military electrical specifications
Integrated Device Technology, Inc.
drain output and requires pullup
resistor of 270 .
IDT7140 (SLAVE):
resistor of 270 .
output flag on IDT7130;
BUSY
BUSY
I/O
is input.
0L
BUSY
- I/O
is open
R/
INT
OE
CE
A
A
W
0L
7L
L
9L
L
L
(1,2)
(2)
L
L
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
BUSY
HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM
input on IDT7140
Decoder
Address
R/
CE
OE
W
L
L
L
10
Control
I/O
6.01
ARBITRATION
DESCRIPTION
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-
Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
low standby power mode.
nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200 W from a 2V battery.
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-
STD-883, Class B, making it ideally suited to military tem-
perature applications demanding the highest level of per-
formance and reliability.
INTERRUPT
MEMORY
ARRAY
LOGIC
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Both devices provide two independent ports with sepa-
Fabricated using IDT's CMOS high-performance tech-
The IDT7130/IDT7140 devices are packaged in 48-pin
, permits the on chip circuitry of each port to enter a very
and
Control
I/O
10
Address
Decoder
CE
OE
R/
W
R
R
R
2689 drw 01
IDT7130SA/LA
IDT7140SA/LA
R/
OE
BUSY
CE
I/O
INT
OCTOBER 1996
A
A
W
R
R
9R
0R
R
0R
R
R
(2)
-I/O
(1,2)
7R
DSC-2689/7
1

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IDT7130SA55P Summary of contents

Page 1

... Both devices provide two independent ports with sepa- rate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled permits the on chip circuitry of each port to enter a very low standby power mode. ...

Page 2

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS PIN CONFIGURATIONS (1, BUSY INT ...

Page 3

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial (2) V Terminal Voltage –0.5 to +7.0 TERM with Respect to GND T Operating 0 to +70 A Temperature T Temperature –55 ...

Page 4

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Test Conditions CE I Dynamic Operating CC L Current (Both Ports Outputs open, Active) f ...

Page 5

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DATA RETENTION WAVEFORM TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775 ...

Page 6

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Enable ...

Page 7

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE DATA OUT I CC CURRENT I SS NOTES: 1. Timing depends on which signal is asserted last, 2. Timing ...

Page 8

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/ ADDRESS (4) DATA OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO. 2, ...

Page 9

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Busy Timing (For Master lDT7130 Only) BUSY t Access Time from Address BAA BUSY t ...

Page 10

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE WITH W R/ 'A' BUSY ' 'B' NOTES must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 ...

Page 11

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Interrupt Timing t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set ...

Page 12

... Port Disabled and in Power- Down Mode Mode DATA Data on Port Written Into Memory DATA Data in Memory Output on Port OUT High Impedance Outputs NOTES – – 10L 0R 10R BUSY data is not written. BUSY data may not be valid, see 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE ...

Page 13

... R = IL, INT the right port interrupt flag ( ) is asserted when the left port R writes to memory location 3FF (HEX) and to clear the interrupt INT flag ( ), the right port must access the memory location R 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since addressable SRAM location. If the interrupt ...

Page 14

IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ORDERING INFORMATION IDT XXXX A 999 Device Type Power Speed Package A A Process/ Temperature Range Commercial ( +70 C) Blank Military (– +125 ...

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