IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 7

• Manufacturer Part Number: IDT7130SA55P
• Description: IC SRAM 8KBIT 55NS 48DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT7130SA55P

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-DIP
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 48
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7130SA55P

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
NOTES:
1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
2. 0 C to +70 C temperature range only, PLCC and TQFP packages.
3. For MASTER/SLAVE combination, t
4. If
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
NOTES:
1. Timing depends on which signal is asserted last,
2. Timing depends on which signal is deaserted first,
3. R/
4. Start of valid data depends on which timing becomes effective last t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Write Cycle
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
data to be placed on the bus for the required t
write pulse can be as short as the specified t
device characterization but is not production tested.
CURRENT
OE
W
DATA
= V
is low during a R/
IH
OUT
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
Data Hold Time
Write Enabled to Output in High-Z
Output Active From End-of-Write
I
I
and the address is valid prior to or coincidental with
CC
SS
W
Parameter
controlled write cycle, the write pulse width must be the larger of t
(3)
(4)
(1)
WC
= t
BAA
t
PU
WP
+ t
DW
.
(1)
WP
(1)
. If
OE
OE
, since R/
50%
OE
or
or
CE
is High during a R/
t
CE
LZ
.
Min.
7130X20
t
20
15
15
15
10
.
—
—
ACE
W
(1)
0
0
0
0
CE
= V
t
LZ
transition Low.
IL
Max.
10
10
—
—
—
—
—
—
—
—
—
AOE
t
must occur after t
AOE
(1)
(2)
6.01
, t
ACE
(4)
7130X25
7140X25
W
Min. Max.
25
20
20
15
12
—
—
, t
0
0
0
0
controlled write cycle, this requirement does not apply and the
AA
, and t
10
10
—
—
—
—
—
—
—
—
—
(6)
(6)
BAA.
BDD
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(3)
.
Min.
WP
35
30
30
25
15
—
—
7130X35
7140X35
0
0
0
0
or (t
(5)
WZ
Max. Min.
—
—
—
—
—
—
—
15
—
15
—
VALID DATA
+ t
DW
) to allow the I/O drivers to turn off
55
40
40
30
20
—
—
7130X55
7140X55
0
0
0
0
t
t
PD
HZ
(4)
(2)
Max.
25
25
—
—
—
—
—
—
—
—
—
t
HZ
50%
(2)
Min. Max.
7130X100
7140X100
100
90
90
55
40
—
—
0
0
0
0
40
40
—
—
—
—
—
—
—
—
—
2689 drw 09
2689 tbl 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7