IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet

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IDT7130SA55P

Manufacturer Part Number
IDT7130SA55P
Description
IC SRAM 8KBIT 55NS 48DIP
Manufacturer
IDT, Integrated Device Technology Inc
Series
-r
Datasheets

Specifications of IDT7130SA55P

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-DIP
Density
8Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
48
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7130SA55P

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0
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
I/O
Features
Functional Block Diagram
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
2. Open drain output: requires pullup resistor.
©2008 Integrated Device Technology, Inc.
0L
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
– IDT7130/IDT7140LA
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
IDT7140 (SLAVE): BUSY is input.
BUSY
- I/O
R/W
Active: 550mW (typ.)
Standby: 5mW (typ.)
Active: 550mW (typ.)
Standby: 1mW (typ.)
INT
OE
CE
A
A
7L
9L
0L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
10
Control
I/O
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
ARBITRATION
INTERRUPT
MEMORY
ARRAY
LOGIC
and
1
On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Control
I/O
10
Address
Decoder
R/W
CE
OE
R
R
R
OCTOBER 2008
IDT7130SA/LA
IDT7140SA/LA
2689 drw 01
OE
CE
R/W
I/O
BUSY
A
A
INT
DSC-2689/14
9R
0R
R
0R
R
R
R
(2)
-I/O
R
(1,2)
7R
,

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IDT7130SA55P Summary of contents

Page 1

... Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin PLCC, and 64-pin STQFP and TQFP Green parts available, see ordering information I/O I/O Control Control MEMORY ARRAY 10 ARBITRATION and INTERRUPT LOGIC 1 IDT7130SA/LA ...

Page 2

... Both devices provide two independent ports with separate con- trol, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry Pin Configurations ...

Page 3

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Pin Configurations (1,2,3) 01/08/02 INDEX I/O 0L I/O 1L I/O 2L I/O ...

Page 4

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias Storage -65 ...

Page 5

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating CC L Current Outputs Disabled (Both Ports Active) ( ...

Page 6

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Data Retention Characteristics Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) t Operation Recovery ...

Page 7

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775Ω Figure 1. Output Test Load 5V BUSY or ...

Page 8

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE ...

Page 9

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT NOTES and is OE ...

Page 10

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter WRITE CYCLE (3) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to ...

Page 11

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) ADDRESS R/W (4) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2, (CE ...

Page 12

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (For MASTER IDT 7130) BUSY Access Time from Address t BAA BUSY Disable Time from Address ...

Page 13

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" "A " DATA IN"A" (1) t APS ADDR "B" BUSY "B" DATA OUT"B" NOTES ensure ...

Page 14

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR AND 'A' 'B' CE 'B' (2) t APS CE 'A' BUSY 'A' Timing Waveform by BUSY Arbitration Controlled by Address ...

Page 15

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical characteristics Over the Operating Temperature and Supply Voltage Range Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t ...

Page 16

... LOW regardless of actual logic level on R the pin. Military, Industrial and Commercial Temperature Ranges Port Disabled and in Power-Down Mode Power-Down Mode (2) Data on Port Written into Memory IN (3) Data in Memory Output on Port OUT High Impedance Outputs timing. DDD (1,4) Right Port INT CE R ...

Page 17

... R memory location 3FF (HEX) and to clear the interrupt flag (INT right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since addressable SRAM location. If the interrupt function is not used, address locations 3FE and 3FF are not used as mail boxes, but as part of the random access memory ...

Page 18

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Ordering Information XXXX A 999 Device Type Power Speed Package NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts ...

Page 19

IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Datasheet Document History (cont'd) 01/08/02: Page 5, 8, 10, 12, & 14 Page 5, 8, 10, 12, & 14 Page 18 Page 1 & 19 01/11/06: Page 1 Page 18 ...

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