IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 6

• Manufacturer Part Number: IDT7130SA55P
• Description: IC SRAM 8KBIT 55NS 48DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT7130SA55P

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-DIP
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 48
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7130SA55P

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
NOTES:
1. Transition is measured 500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0 C to +70 C temperature range. PLCC and TQFP package.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
Read Cycle
NOTES:
1. R/
2. t
3. Start of valid data depends on which timing becomes effective last t
Symbol
ADDRESS
DATA
BUSY
t
t
t
t
t
t
t
t
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
address location. For simultaneous read operations,
BDD
W
OUT
= V
delay is required only in the case where the opposite port is completing a write operation to the same the
OUT
Address Access Time
Output High-Z Time
Read Cycle Time
Chip Enable Access Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time
IH
,
CE
PREVIOUS DATA VALID
= V
IL
, and is
Parameter
OE
(1,4)
(1,4)
= V
t
OH
IL
. Address is valid prior to the coincidental with
t
AA
(4)
(4)
BUSY
t
RC
has no relationship to valid output data.
t
BDD
AOE
(2,3)
7130X20
Min. Max.
6.01
, t
20
—
—
—
—
0
3
0
ACE
, t
—
20
20
11
—
—
10
—
20
DATA VALID
AA
(2)
, and t
7130X25
7140X25
Min. Max. Min. Max. Min. Max. Min.
25
—
—
—
—
—
CE
3
0
0
BDD
MILITARY AND COMMERCIAL TEMPERATURE RANGES
transition Low.
.
(1)
25
25
12
10
25
—
—
—
—
(5)
(5)
(3)
35
—
—
—
—
—
7130X35
7140X35
3
0
0
t
OH
35
35
20
15
35
—
—
—
—
7130X55
7140X55
55
—
—
—
—
—
3
5
0
—
55
55
25
—
—
25
—
50
7130X100
7140X100
100
—
—
—
10
—
—
5
0
2689 drw 08
Max. Unit
100
100
40
40
50
—
—
—
—
2689 tbl 09
ns
ns
ns
ns
ns
ns
ns
ns
ns
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