IDT71321 Integrated Device Technology, IDT71321 Datasheet
IDT71321
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IDT71321 Summary of contents
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... Two flags for port-to-port communications INT • MASTER IDT71321 easily expands data bus width to 16- or-more-bits using SLAVE IDT71421 • On-chip port arbitration logic (IDT71321 only) • output flag on IDT71321; BUSY BUSY • ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS PIN CONFIGURATIONS (1,2) NDEX IDT71321/421 J52 PLCC TOP VIEW ( ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Test Conditions I Dynamic Operating and Current (Both Ports Outputs open, Active MAX I Standby Current and CE SB1 L (Both Ports - TTL ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DATA RETENTION CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data CDR Retention Time (3) t Operation Recovery R Time NOTES 2V +25 C, and is not production tested. ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE CE OE DATA OUT I CC CURRENT I SS NOTES: 1. Timing depends on which signal is asserted last, 2. Timing depends on which signal is deaserted first and the address is valid prior to or coincidental with IH 4 ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/ ADDRESS DATA (4) OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO ADDRESS CE ( DATA IN NOTES must be High during all address transitions. ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Busy Timing (For Master lDT71321 Only) BUSY t Access Time from Address BAA BUSY t Disable Time from Address BDA BUSY ...
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... R NOTES: BUSY 1. t must be met for both Input (IDT71421, slave) or Output (IDT71321, master). WH BUSY 2. is asserted on port 'B' blocking R/ 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'. ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Interrupt Timing t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTE: 1. " ...
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... L L (2) MATCH NOTES: BUSY BUSY 1. Pins and are both outputs for IDT71321 (master). Both are L R BUSY inputs for IDT71421 (slave). outputs on the IDT71321 are open X drain, not push-pull outputs. On slaves the writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port ...
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... L inhibit signal. Thus on the IDT71321/IDT71421 RAMs the Busy pin is an output if the part is Master (IDT71321), and the Busy pin is an input if the part is a Slave (IDT71421) as shown in Figure " ...
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... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ORDERING INFORMATION IDT XXXX A 999 Device Type Power Speed A A Package Process/ Temperature Range Blank 71321 71421 6.03 COMMERCIAL TEMPERATURE RANGE Commercial ( +70 C) 52-pin PLCC (J52-1) ...