IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 9

• Manufacturer Part Number: IDT7130SA55P
• Description: IC SRAM 8KBIT 55NS 48DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT7130SA55P

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-DIP
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 48
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7130SA55P

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
NOTES:
1. Com'l Only, 0 C to +70 C temperature range. PLCC and TQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
3. To ensure that the earlier of the two ports wins.
4. t
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages.
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
NOTES:
1. To ensure that the earlier of the two ports wins. t
2.
3. OE = V
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Symbol
DATA
Busy Timing (For Master lDT7130 Only)
t
t
t
t
t
t
t
t
t
Busy Timing (For Slave IDT7140
t
t
t
t
BDD
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
WB
WH
WDD
DDD
DATA
CE
ADDR
BUSY
ADDR
L
is a calculated parameter and is the greater of 0, t
R/
OUT’B’
=
W
IN’A’
CE
IL
Write Pulse to Data Delay
Arbitration Priority Set-up Time
Write to
Write Pulse to Data Delay
BUSY
BUSY
BUSY
Write Hold After
Write Hold After
BUSY
Write Data Valid to Read Data Delay
BUSY
Write Data Valid to Read Data Delay
’A’
’B’
’B’
for the reading port.
’A’
R
= V
IL.
Access Time from Address
Disable Time from Address
Access Time from Chip Enable
Disable Time from Chip Enable
Disable to Valid Data
BUSY
Input
Parameter
BUSY
BUSY
(5)
t
APS
(6)
(6)
(1)
(2)
(2)
Only)e
(4)
(3)
BDD
(2)
(2)
is ignored for slave (IDT7140).
WDD
– t
WP
MATCH
(actual), or t
7130X20
t
Min. Max.
WC
12
12
—
—
—
—
—
—
—
—
—
5
5
0
6.01
20
20
20
20
—
40
30
—
25
—
—
—
40
30
(1)
DDD
t
WP
7130X25
7140X25
Min. Max. Min. Max.
– t
—
—
—
—
15
—
—
—
15
—
—
5
5
0
DW
(actual).
MATCH
20
20
20
20
50
35
35
50
35
MILITARY AND COMMERCIAL TEMPERATURE RANGES
—
—
—
—
—
(9)
(9)
VALID
t
DW
t
t
7130X35
7140X35
WDD
(7)8
20
20
BDA
—
—
—
—
—
—
—
—
—
5
5
0
M824S258M824S30
BUSY
BUSY
BUSY
BUSY
BUSY
20
20
20
20
60
35
35
60
35
—
—
—
—
—
t
DDD
7130X55
7140X55
Min. Max. Min. Max.
20
20
—
—
—
—
—
—
—
—
—
5
5
0
(2,3,4)
t
DH
t
30
30
30
30
80
55
50
80
55
—
—
—
—
—
BDD
7130X100
7140X100
20
20
—
—
—
—
—
—
—
—
—
5
5
0
7132158M824S4
120
100
120
100
50
50
50
50
65
—
—
—
—
VALID
BUSY
2689 drw 12
2689 tbl 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
."