IDT7130 Integrated Device Technology, IDT7130 Datasheet

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IDT7130

Manufacturer Part Number
IDT7130
Description
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
Manufacturer
Integrated Device Technology
Datasheet

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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
FEATURES
• High-speed access
• Low-power operation
• MASTER IDT7130 easily expands data bus width to
• On-chip port arbitration logic (IDT7130 Only)
• Interrupt flags for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention (LA only)
• TTL-compatible, single 5V 10% power supply
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86875
• Industrial temperature range (–40 C to +85 C) is avail-
NOTES:
1. IDT7130 (MASTER):
2. Open drain output: requires pullup
FUNCTIONAL BLOCK DIAGRAM
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP
—IDT7130/IDT7140SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT7130/IDT7140LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
16-or-more-bits using SLAVE IDT7140
BUSY
able, tested to military electrical specifications
Integrated Device Technology, Inc.
drain output and requires pullup
resistor of 270 .
IDT7140 (SLAVE):
resistor of 270 .
output flag on IDT7130;
BUSY
BUSY
I/O
is input.
0L
BUSY
- I/O
is open
R/
INT
OE
CE
A
A
W
0L
7L
L
9L
L
L
(1,2)
(2)
L
L
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
BUSY
HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM
input on IDT7140
Decoder
Address
R/
CE
OE
W
L
L
L
10
Control
I/O
6.01
ARBITRATION
DESCRIPTION
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-
Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
low standby power mode.
nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200 W from a 2V battery.
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-
STD-883, Class B, making it ideally suited to military tem-
perature applications demanding the highest level of per-
formance and reliability.
INTERRUPT
MEMORY
ARRAY
LOGIC
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Both devices provide two independent ports with sepa-
Fabricated using IDT's CMOS high-performance tech-
The IDT7130/IDT7140 devices are packaged in 48-pin
, permits the on chip circuitry of each port to enter a very
and
Control
I/O
10
Address
Decoder
CE
OE
R/
W
R
R
R
2689 drw 01
IDT7130SA/LA
IDT7140SA/LA
R/
OE
BUSY
CE
I/O
INT
OCTOBER 1996
A
A
W
R
R
9R
0R
R
0R
R
R
(2)
-I/O
(1,2)
7R
DSC-2689/7
1

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IDT7130 Summary of contents

Page 1

... STATIC RAM DESCRIPTION The IDT7130/IDT7140 are high-speed Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM "MASTER" Dual- Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MAS- ...

Page 2

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS PIN CONFIGURATIONS (1, BUSY INT IDT7130 IDT7140 A P48 & C48 DIP 7L TOP VIEW ( I ...

Page 3

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial (2) V Terminal Voltage –0.5 to +7.0 TERM with Respect to GND T Operating 0 to +70 A Temperature T Temperature –55 to +125 BIAS Under Bias T Storage –55 to +125 STG Temperature I DC Output ...

Page 4

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Test Conditions CE I Dynamic Operating CC L Current (Both Ports Outputs open, Active MAX CE I Standby Current SB1 L (Both Ports - TTL ...

Page 5

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DATA RETENTION WAVEFORM TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775 Figure 1. Output Test Load 5V BUSY INT ...

Page 6

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time ...

Page 7

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE DATA OUT I CC CURRENT I SS NOTES: 1. Timing depends on which signal is asserted last, 2. Timing depends on which signal is deaserted first and the address is valid prior to or coincidental with ...

Page 8

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/ ADDRESS (4) DATA OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO ADDRESS CE ( DATA IN NOTES must be High during all address transitions. ...

Page 9

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Busy Timing (For Master lDT7130 Only) BUSY t Access Time from Address BAA BUSY t Disable Time from Address BDA BUSY ...

Page 10

... R/ 'B' NOTES must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". ...

Page 11

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Interrupt Timing t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1 ...

Page 12

... L L (2) MATCH NOTES: BUSY BUSY 1. Pins and are both outputs for IDT7130 (master). Both are L R BUSY inputs for IDT7140 (slave). outputs on the IDT7130 are open drain, X BUSY not push-pull outputs. On slaves the 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port ...

Page 13

... L inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy pin is an output if the part is Master (IDT7130), and the Busy pin is an input if the part is a Slave (IDT7140) as shown in Figure ...

Page 14

... IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ORDERING INFORMATION IDT XXXX A 999 Device Type Power Speed Package A A Process/ Temperature Range Commercial ( +70 C) Blank Military (– +125 C) B Compliant to MIL-STD-883, Class B P 48-pin Plastic DIP (P48-1) ...

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