MT46V256M4TG-75:A Micron Technology Inc, MT46V256M4TG-75:A Datasheet - Page 70
![IC DDR SDRAM 1GBIT 7.5NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V256M4TG-75:A
Manufacturer Part Number
MT46V256M4TG-75:A
Description
IC DDR SDRAM 1GBIT 7.5NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V256M4TG-75:A
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (256M x 4)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure 42:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
Address
DQS
DQS
DQS
WRITE-to-READ – Odd Number of Data, Interrupting
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Notes:
Bank a,
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command
t
the last two data elements).
will not mask these data elements.
WTR is referenced from the first positive CK edge after the last desired data-in pair (not
DI
b
NOP
DI
T1
b
DI
b
T1n
NOP
T2
t WTR
70
T2n
Bank a,
READ
Col n
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
CL = 2
CL = 2
CL = 2
T4
NOP
1Gb: x4, x8, x16 DDR SDRAM
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
T5
NOP
DO
DO
DO
n
n
n
T5n
Operations
T6
NOP
Don’t Care
T6n
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