LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 56

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express DMA Demos
LatticeECP2M PCI Express Development Kit User’s Guide
Figure 13: DMA Demo Block Diagram
Scatter-Gather DMA Overview
Hardware devices perform Direct Memory Access (DMA) by initiating read/
write bus transactions. DMA means transferring data to and from system
memory directly, without involving the CPU.
Bus Master DMA means the device (the PCIe Core on the board) is
controlling the bus and doing the data transfers. In order to perform the
transfer, an address is needed and a length. The SGDMA is configured by the
software driver. The addresses known to software for describing a buffer's
location in memory are only relevant in the domain of the CPU. The CPU (and
software) view memory as virtual 2 GB address spaces per process - the
DMA needs physical memory addresses.
When software allocates a large buffer of memory, the memory manager finds
the number of required free pages (4KB per page) in system memory and
makes them appear contiguous to software via virtual memory translation
tables in hardware. A 1MB buffer alocated by user software appears
contiguous to the software, but in reality is scattered throughout physical
system memory in discontinuous 4KB chunks. The magic of virtual memory
makes it appear contiguous to software.
Demonstrate Windows driver and system programming so users can
extend software for their own particular system needs
System memory allocation (Memory Descriptor Lists)
Interrupt handling - ISRs and DPCs
DMA Demo Operations Overview
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