LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 49

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Throughput Demo
LatticeECP2M PCI Express Development Kit User’s Guide
Table 10: Run Test Page Feature Descriptions
Feature
Cycles
ICG
Controls
Performance
Information Description
This control is only available when the Cycle mode has
been selected. This controls the number of times the
tx_fifo is looped before ending the test. The software
starts the SFIF and waits one second while the SFIF
transfers data (number of cycles). After one second, the
software stops the SFIF and displays the performance.
This has the effect of limiting cycles tests to a maximum
of one second of operation. The cycles value cannot be
larger than 65535 (it is a 16-bit counter).
In Throughput mode this control is not used. In
Throughput mode the SFIF is looping the tx_fifo
continuously until the user presses the STOP button.
(Inter Cycle Gap) This control sets the number of
125MHz clock cycles between cycles. You can use this
control to model TLP traffic patterns that may be
appropriate for your system. The ICG value cannot be
larger than 65535 (it is a 16-bit counter).
Stops and starts test. Status shows an image of a
running man to indicate test is in progress.
Displays the current data rates and other statistics. Data
rates are displayed as progress bars, with the rate (MB/
sec) displayed in the bar. The bars are updated every
second when running in Throughput mode or upon
completion in Cycle mode. The rates are computed from
the hardware counters in the SFIF.
In Throughput mode performance is recalculated every
second and the counters are reset. In Cycles mode the
performance is calculated once at the end of the run
displaying the results for the entire transfer.
Write rates are computed from the following SFIF
hardware counters: Tx TLP Count and Elapsed
Count.
Write Rate (MB/sec) = (Tx TLP Count * TLP Size) /
(Elapsed Count * 8ns)
Read rates are computed from the following SFIF
hardware counters: Rx TLP Count and CplD
Timestamp.
Read Rate (MB/sec) = (Rx TLP Count * RCB_Size) /
(Elapsed Count * 8ns)
RCB_Size is the size in bytes of a CplD.
Running the Throughput Demo
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