LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 51

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Throughput Demo
LatticeECP2M PCI Express Development Kit User’s Guide
Figure 12: Throughput Demo View Memory Page
See the Table 11 below for details about features on the View Memory page
Table 11: View Memory Page Sub Tab Descriptions
Sub Tab Page
PC Mem Buf
SFIF Rx FIFO
Known Issues
Currently there is only one known issue that should be considered when
exercising the Throughput demo. The Throughput reference design has a
difficult time meeting timing constraints when using a -6 speed grade. If you
rebuild the Throughput reference design, a -7 speed grade is recommended.
Information Description
The PC system memory buffer sub tab allows you to
inspect the contents of the PC’s system memory buffer
allocated in the kernel space by the driver and is used
for the source of MRd requests and destination for MWr
TLPs. This can also be used to verify that the MWr TLPs
have worked and that the data was transferred from the
PCI Express solutions board into system memory.
The SFIF Rx FIFO sub tab displays the parsed and
formatted contents of the SFIF rx_fifo. This can be used
to verify that a small burst of MRd TLPs have returned
the proper data to the solutions board. The TLPs are
parsed and time stamped.
Running the Throughput Demo
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