LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 55

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express DMA Demos
DMA Demo Operations Overview
LatticeECP2M PCI Express Development Kit User’s Guide
Direct Memory Access (DMA) is a method of transferring data from one
memory mapped device to another. The data is transferred by a dedicated
device that performs the bus cycle (memory reads and writes). The CPU is
not involved in the actual data movement.
Using a dedicated DMA device frees the CPU to do other operations and also
shortens the transfer time. If the CPU had to move the data, it would be done
in a software loop which requires fetching, decoding and executing each
instruction involved in the loop. This could easily expand to 10 or more
instruction cycles per datum moved. A DMA engine could perform the same
datum move operation in 1 to 3 bus clocks (depending on bus architecture).
In modern PC systems the DMA engine, the device responsible for
performing the bus cycles to implement the transfer, is located on the add-in
card. This is known as Bus Master DMA and is the preferred method of
operation. The PCI bus is being phased out and replaced with the PCIe bus.
To take advantage of the high bandwidth that PCIe offers, DMA is used to
transfer the data between the add-in card and the system memory. The
Lattice SGDMAC IP works in conjunction with the Lattice PCIe IP core to
transport the data.
The Scatter-Gather DMA (SGDMA) IP core, together with the PCIe IP core,
demonstrates moving data between the Lattice FPGA and PC system
memory using a Lattice PCI Express solutions board. The board uses the PCI
Express link as both control (setup and operation of the core) and data path
(DMA to/from PC system memory). The PC provides the test platform (power,
run-time environment) and the user interface.
A PC platform is used because currently PCs are the only readily available,
economical and standard platform utilizing PCIe. A Windows device driver
provides the interface to the board’s register and memory space. Application
software uses the driver to setup and configure the DMA engine, execute it,
and verify the results. The demo system is illustrated in the block diagram in
Figure 13 on page 48.
The demo hardware has the following objectives:
The demo application software has the following objectives:
Acts as a reference design for using the PCIe and SGDMA IP cores
Performs actual DMA transfers over the PCIe bus at an optimal rate
Provides counters and timers to measure performance
Provides a platform for demonstration and experimentation
Demonstrates accessing, configuring and operating the PCIe and
SGDMA IP cores
Verifies proper operation (ensures all DMA data is transferred from source
to destination un-corrupted)
DMA Demo Operations Overview
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