LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 35

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Basic Demo
LatticeECP2M PCI Express Development Kit User’s Guide
Figure 6: PCIe Basic Demo Memory Page
The following table provides descriptions of all of the Memory page features.
Table 6: Memory Page Features
Feature
Pattern Tests
READ
CLEAR
FILL
memory interface. See Table 6, "Memory Page Features" on page 27 to
see what actions can be performed in this page.
Description
Pressing Run starts a test to check that all locations of
the EBR can be read and written and that the contents
are correct. First, all 16KB are cleared to 0 and verified.
Then various patterns (AA, 55, 01, FF) are written to all
locations and verified. If everything passes, PASS is
displayed. If a memory location has an incorrect value
the test aborts and displays ERRORS! The memory
contents are left with an incrementing pattern 00 01 02...
that is displayed when the test successfully finishes.
The contents of the EBR memory are read from the
value entered in the offset field. 256 bytes are read and
displayed in the list box above.
Sets all 16KB to 0.
Writes the byte value entered in the field to all 16KB
locations.
Touring the PCIe Basic Demo Interface
27