LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 47

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Throughput Demo
LatticeECP2M PCI Express Development Kit User’s Guide
See the Table 10, “Run Test Page Feature Descriptions” below for details
about features on the 16 Segment Control page.
Table 10: Run Test Page Feature Descriptions
Feature
Setup
Test Mode
TLP Types
There are two modes of operation, cycles and
Information Description
Sets the configuration for the specific test.
throughput.
The key difference between the two modes is how the
performance data is displayed. A throughput test will
provide new performance data every second. A cycle
test will provide performance data after the number of
cycles completes, or one second, whichever comes first.
Note that cycles will not run longer than one second.
Cycles tests run once; throughput tests run continuously
until stopped.
There are four types of TLP types which impact the type
of “traffic” sent over the PCI Express link.
Throughput - This mode allows the test to run
continuously looping through the tx_fifo and updating
the performance numbers every second. This test
will run until the you click the STOP button.
Cycles - This mode allows you to set up a specific
number of times the tx_fifo will be looped. Once
complete, the test will stop automatically and the
performance numbers will be displayed based on the
entire run. The cycle consists of all MRd TLPs or all
MWr TLPs. The purpose is to validate that the
correct number of TLPs was sent/received using the
counters and View Memory page. See TLP Types in
this table for descriptions.
MWr – Memory Write TLPs to write data from the
endpoint to the PC system memory.
MRd – Memory Read TLPs to read data from PC
system memory to the endpoint.
MRd+MWr – Both Memory Read and Memory Write
TLPs are sent to the root complex.
R+W+Ctl – Read, Write, and Control data are
present on the PCI Express link. The Read and Write
TLPs are sent from the SFIF while the PC is also
modifying the GPIO 16-segment display LEDs. This
TLP type shows both data and control plane TLPs
sharing the PCI Express link.
Running the Throughput Demo
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