LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 30

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Basic Demo
Resource References
Basic Demo Operations Overview
LatticeECP2M PCI Express Development Kit User’s Guide
Please be aware of the specific companion documentation for supplementing
your knowledge when using this demo:
Hardware Resources
The PCIe Basic Demo x1 bitstream is built from the ispLEVER project located
in Hardware\PCIex1\ecp2m50_PCIeBASIC_SBx1\Implementation\
ecp2m50_PCIeBasic_SBx1 directory. The Verilog source code is located in
the project Source\ directory.
The Verilog design architecture is explained in Documentation\ECP2M PCI
Express Basic Reference Design User Guide\UG15.pdf. This document
describes the purpose and functionality of the Verilog modules used in PCIe
Basic Demo design.
Software Resources
The PCIe Basic Demo uses the lscpcie2.sys device driver. The source code
for this device driver is located in Software\lscpcie2_Win2kXP\drvr. The
architecture of the lscpcie2 device driver is explained in the “lscpcie2 Driver
Reference Manual” which can be accessed through the Software\
PCIeDocIndex.html link.
The PCIe Basic Demo application source code is located in
Software\PCIeBasic_Win2kXP\BasicGUI\DemoUI. This directory contains the
Java project source code to create the user interface. The GUI also uses the
PCIeAPI_Lib_Win2kXP API library.
The architecture of the PCIe Basic Demo application is explained in the “PCIe
Basic Demo Reference Manual” and “PCIe API Reference Manual” which can
be accessed through the Software\ PCIeDocIndex.html link.
The PCIe Basic demo shows the capabilities of the Lattice FPGA and the PCI
Express IP core functioning in a PCI Express slot in a Windows PC. The
demo is easy to use and requires no test equipment.
This demo software allows you to access memory and registers on the board
and provides real-time interaction with the solutions board hardware to
demonstrate a functional PCI Express communications path between the
application and driver software (running on the PC CPU) and the FPGA IP.
Device driver and application source code are available so you can modify
and extend the behavior of the tests or use them as a starting point for new
PCIe designs.
If you experience any problems running this demo, please refer to Appendix
B, “Troubleshooting” on page 63.
Resource References
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