LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 45

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Throughput Demo
LatticeECP2M PCI Express Development Kit User’s Guide
Table 9: Device Info Page Sub Tab Descriptions
Sub Tab Page
Driver Info
Config Regs
Capabilities Regs
2. Now click on the Run Test tab to see the contents of the Run Test page.
3. On the Run Test page, under Setup options, select the following:
4. On the Run Test page, click the RUN button. After running your test,
of the sub tabs that you can select and are located at the bottom of the
page dialog.
This page operates the demo design. In this page, you will be running the
demonstration to compute the throughput of the PCI Express link and
display the transfer rates with bar graphs. You can select read, write and
read-write throughput tests. See Figure 11, "Throughput Run Test Info
Page" on page 38.
Test Mode: Thruput
TLP Type: MWr
For the rest of the options, take the defaults.
notice the status indicators in the Performance section at right. The two
top progress indicator bars for MRd (memory read TLPs), and MWr
(memory write TLPs) will contain a percentage of blue which indicates
throughput. The two progress indicator bars below that show the wait time
for the root complex to accept TLPs over the entire time spent running.
Information Description
Provides information about the device driver including
the version, the resources used, and the transfer
information.
The demo design uses the lscpci2 driver. The demo
requests two BARs (Base Address Registers) and a
single interrupt vector. The Xfer Info box provides the
buffer sizes for the root complex for Posted and Non-
Posted TLPs. This information is important when
considering the amount of credit waiting the demo
design demonstrates when running a transfer.
A root complex with larger buffers will provide better
performance when running the demo since it will not
have to release credits as quickly to allow the next TLP.
Provides the standard PCI Type0 space configuration
register contents. Things such as Device ID and Vendor
ID are displayed and the assigned BARs.
Provides the link list of capability structures and their
contents. Key information found in this box is the
maximum TLP size supported by the root complex and
the negotiated link width.
Running the Throughput Demo
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