LFE2M50E-PS-EVN Lattice, LFE2M50E-PS-EVN Datasheet - Page 42

• Manufacturer Part Number: LFE2M50E-PS-EVN
• Description: Programmable Logic IC Development Tools LatticeECP2M PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE2M50E-PS-EVN

• Rohs: yes
• Tool Is For Evaluation Of: LatticeECP2M-50
• Factory Pack Quantity: 1

Running the PCI Express Throughput Demo
Resource References
Throughput Demo Operations Overview
LatticeECP2M PCI Express Development Kit User’s Guide
Please be aware of the specific companion documentation for supplementing
your knowledge when using this demo:
Hardware Resources
The PCIe Throughput Demo x1 bitstream is built from the ispLEVER project
located in Hardware\PCIe x1\ecp2m50_PCIeThruput_SBx1\Implementation
\ecp2m50_PCIeThruput_SBx1. The Verilog source code is located in the
project Source\ directory.
The Verilog design architecture is explained in Documentation\ ECP2M PCI
Express Throughput Reference Design User Guide\UG07.pdf. This document
describes the purpose and functionality of the Verilog modules used in PCIe
Throughput Demo design.
Software Resources
The PCIe Throughput Demo uses the lscpcie2.sys device driver. The source
code for this device driver is located in Software\lscpcie2_Win2kXP\drvr. The
architecture of the lscpcie2 device driver is explained in the “lscpcie2 Driver
Reference Manual” which can be accessed through the Software\
PCIeDocIndex.html link.
The PCIe Throughput Demo application source code is located in
Software\PCIeSFIF_Win2kXP\SFIF_GUI\SFIF_UI. This directory contains the
Java project source code to create the user interface. The GUI also uses the
PCIeAPI_Lib_Win2kXP API library.
The architecture of the PCIe Throughput Demo application is explained in the
“PCIe Thruput Demo Reference Manual” and “PCIe API Reference Manual”
which can be accessed through the Software\ PCIeDocIndex.html link.
The purpose of this demo is to show the performance of the Lattice PCI
Express SERDES hardware and PCI Express IP core when operating in a PC
PCI Express expansion slot. The data rates for writes to the PC system
memory and reads from the PC system memory are measured and displayed
in a graphical user interface.
The demo performs Direct Memory Access (DMA) operations by transferring
data directly to and from the PC memory. The demo uses an IP block named
the SFIF (Stored FIFO InterFace) to generate read and write Transaction
Layer Packets (TLPs) that will access the PC system memory. The SFIF
exercises the PCI Express IP core and link with low overhead so the true
performance of the PCI Express core and link can be measured.
The PCI Express interface is used for both control plane and data plane
traffic. The control plane loads the SFIF memory and sets up the transfer. The
Resource References
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