DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 7

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

DS26519 16-Port T1/E1/J1 Transceiver
LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14
Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15
Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16
Table 8-1. Detailed Pin Descriptions ......................................................................................................................... 20
Table 9-1. CLKO Frequency Selection ...................................................................................................................... 37
Table 9-2. Reset Functions........................................................................................................................................ 38
Table 9-3. Registers Related to the Elastic Store...................................................................................................... 43
Table 9-4. Elastic Store Delay After Initialization....................................................................................................... 44
Table 9-5. Registers Related to the IBO Multiplexer ................................................................................................. 46
Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0).................................................................................. 50
Table 9-7. RSIGn Output Pin Definitions (GTCR1.GIBO = 0) ................................................................................... 51
Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) ..................................................................................... 52
Table 9-9. TSIGn Input Pin Definitions (GTCR1.GIBO = 0) ...................................................................................... 53
Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) ................................................................................ 54
Table 9-11. D4 Framing Mode................................................................................................................................... 58
Table 9-12. ESF Framing Mode ................................................................................................................................ 59
Table 9-13. SLC-96 Framing ..................................................................................................................................... 59
Table 9-14. E1 FAS/NFAS Framing .......................................................................................................................... 61
Table 9-15. Registers Related to Setting Up the Framer .......................................................................................... 62
Table 9-16. Registers Related to the Transmit Synchronizer.................................................................................... 63
Table 9-17. Registers Related to Signaling ............................................................................................................... 64
Table 9-18. Registers Related to SLC-96.................................................................................................................. 67
Table 9-19. Registers Related to T1 Transmit BOC.................................................................................................. 69
Table 9-20. Registers Related to T1 Receive BOC................................................................................................... 69
Table 9-21. Registers Related to T1 Transmit FDL................................................................................................... 70
Table 9-22. Registers Related to T1 Receive FDL.................................................................................................... 70
Table 9-23. Registers Related to E1 Data Link ......................................................................................................... 71
Table 9-24. Registers Related to Maintenance and Alarms...................................................................................... 73
Table 9-25. T1 Alarm Criteria .................................................................................................................................... 75
Table 9-26. Registers Related to Transmit RAI (Yellow Alarm) ................................................................................ 75
Table 9-27. Registers Related to Receive RAI (Yellow Alarm) ................................................................................. 76
Table 9-28. T1 Line Code Violation Counting Options .............................................................................................. 77
Table 9-29. E1 Line Code Violation Counting Options .............................................................................................. 77
Table 9-30. T1 Path Code Violation Counting Arrangements ................................................................................... 78
Table 9-31. T1 Frames Out of Sync Counting Arrangements ................................................................................... 78
Table 9-32. Registers Related to DS0 Monitoring ..................................................................................................... 79
Table 9-33. Registers Related to T1 In-Band Loop Code Generator ........................................................................ 81
Table 9-34. Registers Related to T1 In-Band Loop Code Detection ......................................................................... 82
Table 9-35. Register Related to Framer Payload Loopbacks ................................................................................... 83
Table 9-36. Registers Related to the HDLC .............................................................................................................. 84
Table 9-37. Recommended Supply Decoupling ........................................................................................................ 89
Table 9-38. Registers Related to Control of the LIU.................................................................................................. 92
Table 9-39. Telecommunications Specification Compliance for DS26519 Transmitters .......................................... 93
Table 9-40. Transformer Specifications..................................................................................................................... 93
Table 9-41. Receive Impedance Control ................................................................................................................... 97
Table 9-42. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications............................................................ 100
Table 9-43. Jitter Attenuator Standards Compliance............................................................................................... 102
Table 9-44. Registers Related to Configure, Control, and Status of BERT............................................................. 106
Table 10-1. Register Address Ranges (in Hex)....................................................................................................... 108
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