DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 275
DS26519GA2
Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26519GA2.pdf
(310 pages)
Specifications of DS26519GA2
Part # Aliases
90-26519-0A2
- Current page: 275 of 310
- Download datasheet (3Mb)
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
TSSYNCIOn
TSYSCLKn
TCHBLKn
TCHCLKn
TSERn
TSIGn
NOTE 1: TSERn DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.
NOTE 2: TCHBLKn IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1.
NOTE 3: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE
ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1. (NORMALLY THE TRANSMIT-SIDE FORMATTER
OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS THROUGH THE F-BIT
POSITION).
1
2
CHANNEL 31
CHANNEL 31
A
B
C/A D/B
LSB MSB
275 of 310
CHANNEL 32
CHANNEL 32
A
B
C/A D/B
LSB
DS26519 16-Port T1/E1/J1 Transceiver
F
3
CHANNEL 1
CHANNEL 1
A
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