DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 203

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 5: Receive RAI-CI (RRAI-CI)
Bit 4: Receive AIS-CI (RAIS-CI)
Bit 3: Receive SLC-96 (RSLC96)
Bit 2: Receive FDL Register Full (RFDLF)
Bit 1: BOC Clear Event (BC)
Bit 0: BOC Detect Event (BD)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 1: Sa6 Codeword Detect (Sa6CD). This bit will enable the interrupt generated when a valid codeword (per
ETS 300 233) is detected in the Sa6 bits.
Bit 0: SaX Change Detect (SaXCD). This bit will enable the interrupt generated when a change of state is
detected in any of the unmasked SaX bit positions. The masked or unmasked SaX bits are selected by the
E1RSAIMR
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
RIM7
RIM7
register.
—
for E1 Mode
—
for T1 Mode.
7
0
7
0
RIM7 (T1 Mode)
Receive Interrupt Mask Register 7 (BOC:FDL)
0A6h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
RIM7 (E1 Mode)
Receive Interrupt Mask Register 7 (BOC:FDL)
0A6h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
.
—
—
6
0
6
0
RRAI-CI
—
5
0
5
0
RAIS-CI
203 of 310
—
4
0
4
0
RSLC96
—
3
0
3
0
DS26519 16-Port T1/E1/J1 Transceiver
RFDLF
—
2
0
2
0
Sa6CD
BC
1
0
1
0
SaXCD
BD
0
0
0
0