DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 141

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Channels:
Bit #
Name
Default
Bit 2: LIU Software Reset (LRST). LIU Channels 1–8 logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
Bit 1: BERT Software Reset (BRST). BERT Channels 1–8 logic and registers are reset with a 0-to-1 transition in
this bit. The reset is released when a zero is written to this bit.
Bit 0: Framer Software Reset (FRST). Framers 1-8 to logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
Register Name:
Register Description:
Register Address:
Channels:
Bit #
Name
Default
Bit 2: LIU Software Reset (LRST). LIU Channels 9–16 logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
Bit 1: BERT Software Reset (BRST). BERT Channels 9–16 logic and registers are reset with a 0-to-1 transition in
this bit. The reset is released when a zero is written to this bit.
Bit 0: Framer Software Reset (FRST). Framers 9–16 to logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation.
1 = Reset LIU channels 1–8.
0 = Normal operation.
1 = Reset BERT channels 1–8.
0 = Normal operation.
1 = Reset framers 1–8.
0 = Normal operation.
1 = Reset LIU channels 9–16.
0 = Normal operation.
1 = Reset BERT channels 9–16.
0 = Normal operation.
1 = Reset framers 9–16.
—
—
7
0
7
0
GSRR1
Global LIU Software Reset Register 1
00F6h
1 to 8
GSRR2
Global LIU Software Reset Register 2
20F6h
9 to 16
—
—
6
0
6
0
—
—
5
0
5
0
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—
—
4
0
4
0
—
—
3
0
3
0
DS26519 16-Port T1/E1/J1 Transceiver
LRST
LRST
2
0
2
0
BRST
BRST
1
0
1
0
FRST
FRST
0
0
0
0