DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 271

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DS26519GA2

Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26519GA2

Part # Aliases
90-26519-0A2
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode
RSYSCLKn
RSYNCn
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 0).
NOTE 4: SHOWS SYSTEM IMPLEMENATION WITH MULTIPLE DS26519 CORES DRIVING THE BACKPLANE.
NOTE 5: THOUGH NOT SHOWN, RCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD.
NOTE 6: THOUGH NOT SHOWN, RCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.
RSYNCn
RSIGn
RSIGn
RSERn
RSIGn
RSERn
RSERn
1
2
3
1
2
FR2 CH32 FR3 CH32 FR0 CH1
FR2 CH32 FR3 CH32 FR0 CH1
FRAMER 3, CHANNEL 32
FRAMER 3, CHANNEL 32
FR1 CH32
FR1 CH32
A
B
C
LSB
D
FR0 CH1
FR0 CH1
MSB
FR1 CH1
FR1 CH1
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 1
FR2 CH1
FR2 CH1
BIT DETAIL
271 of 310
FR1 CH1
FR1 CH1
A
FR3 CH1
FR3 CH1
B
C
FR0 CH2
FR0 CH2
LSB
D
FR0 CH2
FR0 CH2
MSB
FR1 CH2
FR1 CH2
DS26519 16-Port T1/E1/J1 Transceiver
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
FR2 CH2
FR2 CH2
FR1 CH2
FR1 CH2
A
FR3 CH2
FR3 CH2
B
C
LSB
D

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