DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 5

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

DS26519 16-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ......................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram........................................................................................................................... 19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 34
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 34
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 34
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 34
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 35
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 35
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 35
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 35
Figure 9-9. Backplane Clock Generation................................................................................................................... 36
Figure 9-10. GPIO Mux Control ................................................................................................................................. 40
Figure 9-11. Device Interrupt Information Flow Diagram........................................................................................... 42
Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz .................................................................................... 47
Figure 9-13. IBO Multiplexer Equivalent Circuit—8.192MHz .................................................................................... 48
Figure 9-14. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................. 49
Figure 9-15. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 56
Figure 9-16. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 56
Figure 9-17. CRC-4 Recalculate Method .................................................................................................................. 80
Figure 9-18. HDLC Message Receive Example........................................................................................................ 86
Figure 9-19. HDLC Message Transmit Example....................................................................................................... 88
Figure 9-20. Network Connection—Longitudinal Protection ..................................................................................... 91
Figure 9-21. T1/J1 Transmit Pulse Templates .......................................................................................................... 94
Figure 9-22. E1 Transmit Pulse Templates ............................................................................................................... 95
Figure 9-23. Receive LIU Termination Options ......................................................................................................... 97
Figure 9-24. Typical Monitor Application ................................................................................................................... 98
Figure 9-25. HPS Block Diagram............................................................................................................................. 101
Figure 9-26. Jitter Attenuation ................................................................................................................................. 102
Figure 9-27. Loopback Diagram .............................................................................................................................. 103
Figure 9-28. Analog Loopback................................................................................................................................. 103
Figure 9-29. Local Loopback ................................................................................................................................... 104
Figure 9-30. Remote Loopback 2 ............................................................................................................................ 104
Figure 9-31. Dual Loopback .................................................................................................................................... 105
Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 268
Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 268
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 269
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 269
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 270
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 271
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 272
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 272
Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 273
Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 273
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 274
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 274
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 275
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 276
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 277
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 277
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