DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 272

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit
RSYSCLKn
RSYNCn
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 0).
NOTE 4: SHOWS SYSTEM IMPLEMENATION WITH MULTIPLE DS26519 CORES DRIVING THE BACKPLANE.
NOTE 5: THOUGH NOT SHOWN, RCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD.
NOTE 6: THOUGH NOT SHOWN, RCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.
RSERn
RSYNCn
RSERn
RSIGn
RSIGn
RSERn
RSIGn
RCHCLKn
RSYNCn
RSERn
RCLKn
1
2
2
1
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR1 CH1-32
FR1 CH1-32
FRAMER 3, CHANNEL 32
FRAMER 3, CHANNEL 32
A
B
LSB
C/A D/B
FR0 CH1-32
FR0 CH1-32
LSB
F-BIT
MSB
FRAMER 0, CHANNEL 1
MSB
FRAMER 0, CHANNEL 1
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BIT DETAIL
FR1 CH1-32
FR1 CH1-32
A
B
C/A D/B
LSB
FR0 CH1-32
FR0 CH1-32
MSB
DS26519 16-Port T1/E1/J1 Transceiver
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
A
FR1 CH1-32
FR1 CH1-32
B
C/A D/B
LSB