DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 30

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

SCANMODE
REFCLKIO
TST_RC1
TST_TC1
TST_RA1
TST_RB1
DIGIOEN
SCANEN
TST_TA1
TST_TB1
SPI_SEL
RESETB
JTCLK
NAME
JTRST
MCLK
JTMS
JTDO
WRB /
RWB
INTB
JTDI
BTS
R13
U15
A18
A14
V18
PIN
F11
T16
U9
G4
G5
N6
R6
F5
F4
E3
E4
T6
K1
K2
P6
L2
Impedance
Stateable
Output/
Output,
Output
Output
Pullup
Pullup
Pullup
Pullup
TYPE
Input/
Input,
Input,
Input,
Input,
Input
Input
Input
Input
Input
Input
Input
Input
High
Tri-
Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies
write access to one of the DS26519 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
Interrupt Bar. This active-low output is asserted when an unmasked interrupt
event is detected. INTB will be deasserted (and tri-stated) when all interrupts
have been acknowledged and serviced. Extensive mask bits are provided at the
global level, framer, LIU, and BERT level.
SPI Serial Bus Mode Select
0 = Parallel Bus Mode
1 = SPI Serial Bus Mode
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be tied low.
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See
Reset Bar. Active-low reset. This input forces the complete DS26519 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz
reference clock. This allows for multiple DS26519s to share the same reference
for generation of the backplane clock. Hence, in a system consisting of multiple
DS26519s, one can be a master and others a slave using the same reference
clock.
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to V
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10k Ω resistor
operation. If boundary scan is not used, this pin should be held low.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10k Ω pullup resistor.
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10k Ω pullup resistor.
JTAG Data Out. Test instructions and data are clocked out of this pin on the
falling edge of JTCLK. If not used, this pin should be left unconnected.
Scan Enable. When low, the device is in normal operation. User should tie low.
Scan Mode. When low, normal operational clocks are used to clock the flip flops.
User should tie low.
LIU Test Points. Test signals from LIU 1. User should leave unconnected.
SYSTEM INTERFACE
30 of 310
TEST
Table
10-14.
FUNCTION
DS26519 16-Port T1/E1/J1 Transceiver
DD
for normal operation.