DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 279

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DS26519GA2

Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26519GA2

Part # Aliases
90-26519-0A2
Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RSYSCLKn
RSYNCn
RMSYNCn
RSYNCn
RCHCLKn
RCHBLKn
RSYSCLKn
RCHBLKn
RMSYNCn
RSYNCn
RCHCLKn
RSERn
RSYNCn
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS
MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE).
NOTE 2: RSYNCn IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNCn IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 4: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24.
RSERn
RSIGn
NOTE 1: RSYNCn IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 2: RSYNCn IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 3: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 4: RSIGn NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
2
3
1
4
1
3
2
CHANNEL 23/31
CHANNEL 31
A
CHANNEL 31
B
LSB
C
MSB
LSB MSB
D
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CHANNEL 24/32
CHANNEL 32
A
CHANNEL 32
B
LSB
C
DS26519 16-Port T1/E1/J1 Transceiver
LSB MSB
F
D
MSB
CHANNEL 1
CHANNEL 1/2
CHANNEL 1
Note 4

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