LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 9

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
The Delay Adjust Block adjusts either the delays of the reference or feedback signals. The Delay Adjust Block can
either be programmed during configuration or can be adjusted dynamically. The setup, hold or clock-to-out times of
the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or
delay the output clock with reference to the input clock.
Following the Delay Adjust Block, both the input path and feedback signals enter the Voltage Controlled Oscillator
(VCO) block. In this block the difference between the input path and feedback signals is used to control the fre-
quency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that VCO has locked onto
the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not relock
until the t
edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at a
lower frequency. This is a shared resource which can only be used by one PLL (GPLL or SPLL) per side.
The output of the VCO then enters the post-scalar divider. The post-scalar divider allows the VCO to operate at
higher frequencies than the clock output (CLKOP), thereby increasing the frequency range. A secondary divider
takes the CLKOP signal and uses it to derive lower frequency outputs (CLKOK). The Phase/Duty Select block
adjusts the phase and duty cycle of the CLKOP signal and generates the CLKOS signal. The phase/duty cycle set-
ting can be pre-programmed or dynamically adjusted.
The primary output from the post scalar divider CLKOP along with the outputs from the secondary divider (CLKOK)
and Phase/Duty select (CLKOS) are fed to the clock distribution network.
Figure 2-4. General Purpose PLL (GPLL) Diagram
Standard PLL (SPLL)
Some of the larger devices have two to four Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but
without delay adjustment capability. SPLLs also provide different parametric specifications. For more information,
please see details of additional technical documentation at the end of this data sheet.
Table 2-4 provides a description of the signals in the GPLL and SPLL blocks.
from clock net(CLKOP) or from
(from routing or external pin)
from CLKOP (PLL internal),
a user clock (pin or logic)
LOCK
CLKI
CLKFB
RSTK
RST
parameter has been satisfied. LatticeECP2 devices have two dedicated pins on the left and right
Input Clock
Feedback
(CLKFB)
Divider
Divider
(CLKI)
Dynamic Delay Adjustment
Adjust
Delay
2-6
Controlled
Oscillator
Voltage
(Optional External Capacitor)
PLLCAP External Pin
Post Scalar
(CLKOP)
Divider
LatticeECP2 Family Data Sheet
Dynamic Adjustment
Phase/Duty
Secondary
(CLKOK)
Divider
Select
Architecture
CLKOK
CLKOP
CLKOS
LOCK