LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 8

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Two additional signals: Carry Generate and Carry Propagate are generated per slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating slices.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and
Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit pseudo
dual port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice
as the read-only port.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information on
using RAM in LatticeECP2 devices, please see details of additional technical documentation at the end of this data
sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accom-
plished through the programming interface during PFU configuration.
Routing
There are many resources provided in the LatticeECP2 devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered allowing both short and long connections routing between PFUs.
The LatticeECP2 family has an enhanced routing architecture that produces a compact design. The ispLEVER
design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route
tool is completely automatic, although an interactive routing editor is available to optimize the design.
sysCLOCK Phase Locked Loops (GPLL/SPLL)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP2 family
support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition, some of the larger devices
have two to four Standard PLLs (SPLLs) that have a subset of GPLL functionality.
General Purpose PLL (GPLL)
The architecture of the GPLL is shown in Figure 2-4. A description of the GPLL functionality follows.
CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the
Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP or from a user clock PIN/
logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre-
quency.
– A not-equal-to B
– A less-than-or-equal-to B
Number of slices
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
SPR 16X4
2-5
3
LatticeECP2 Family Data Sheet
PDPR 16X4
3
Architecture