LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 65

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
LatticeECP2 Internal Switching Characteristics
PFU Logic Mode Timing
t
t
t
t
t
t
t
t
PFU Memory Mode Timing
t
t
t
t
t
t
t
PIO Input/Output Buffer Timing
t
t
t
t
t
t
t
t
t
EBR Timing
t
t
t
t
t
t
t
t
LUT4_PFU
LUT6_PFU
LSR_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
SUI_PIO
HI_PIO
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
CO_EBR
COO_EBR
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
HWREN_EBR
Parameter
LUT4 Delay (A to D Inputs to F Output)
LUT6 Delay (A to D Inputs to OFX
Output)
Set/Reset to Output (Asynchronous)
Clock to Mux (M0, M1) Input Setup Time
Clock to Mux (M0, M1) Input Hold Time
Clock to D Input Setup Time
Clock to D Input Hold Time
Clock to Q Delay, (D-type Register
Configuration)
Clock to Output Write (F Port)
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay (LVCMOS25)
Output Buffer Delay (LVCMOS25)
Input Register Setup Time (Data Before
Clock)
Input Register Hold Time (Data After
Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
Set/Reset Hold Time
Clock (Read) to Output from Address or
Data
Clock (Write) to Output from EBR Output
Register
Setup Data to EBR Memory (Write Clk)
Hold Data to EBR Memory (Write Clk)
Setup Address to EBR Memory (Write
Clk)
Hold Address to EBR Memory (Write Clk)
Setup Write/Read Enable to EBR
Memory (Write/Read Clk)
Hold Write/Read Enable to EBR Memory
(Write/Read Clk)
Description
Over Recommended Operating Conditions
3-18
Min.
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-7
Max.
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—
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—
—
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—
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—
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1
DC and Switching Characteristics
LatticeECP2 Family Data Sheet
Min.
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—
—
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—
—
-6
Max.
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—
—
—
—
—
—
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—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
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—
—
—
—
—
—
—
—
—
-5
Max.
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns