LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 42

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
3. Left and Right (Banks 2, 3, 6 and 7) sysIO Buffer Pairs (50% Differential and 100% Single-Ended Outputs)
4. Bank 8 sysIO Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by Configura-
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to
ensure that all other V
all the I/O banks that are critical to the application. For more information on controlling the output logic state with
valid input logic levels during power-up in LatticeECP2 devices, see details of additional technical documentation at
the end of this data sheet.
The V
ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V
together with the V
Supported Standards
The LatticeECP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can
be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V,
1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration
options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,
MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O stan-
dards (together with their supply and reference voltages) supported by LatticeECP2 devices. For further informa-
tion on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical
information at the end of this data sheet.
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-
erenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and
the comp (complementary) pad is associated with the negative side of the differential I/O.
LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
tion)
The sysIO buffers in Bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed
and referenced). The referenced input buffer can also be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the
differential input buffer.
CC
and V
CCAUX
CC
supply the power to the FPGA core fabric, whereas the V
CCIO
and V
banks are active with valid input logic levels to properly control the output logic states of
CCAUX
supplies.
2-39
CC
, V
CCIO
CCIO8
supplies should be powered-up before or
LatticeECP2 Family Data Sheet
and V
CCIO
CCAUX
supplies power to the I/O buff-
have reached satisfactory
Architecture