LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 57

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
LVPECL
The LatticeECP2 devices support the differential LVPECL standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard
is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for
point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions
16mA
16mA
V
V
V
Z
R
R
R
V
V
V
V
Z
I
1. For input buffer, see LVDS table.
DC
CCIO
CCIO
OUT
BACK
CCIO
T
OH
OL
OD
CM
S
P
Parameter
(+/-5%)
(+/-5%)
On-chip
= 3.3V
= 3.3V
R
R
Over Recommended Operating Conditions
Output Driver Supply (+/-5%)
Driver Impedance
Driver Series Resistor (+/-1%)
Driver Parallel Resistor (+/-1%)
Receiver Termination (+/-1%)
Output High Voltage (After R
Output Low Voltage (After R
Output Differential Voltage (After R
Output Common Mode Voltage
Back Impedance
DC Output Current
S
S
1
Off-chip
= 93.1 ohms
= 93.1 ohms
(+/-1%)
(+/-1%)
Description
R
Zo = 100 ohm differential
D
Transmission line,
= 196 ohms
(+/-1%)
3-10
1
1
)
)
1
)
R
T
= 100 ohms
DC and Switching Characteristics
(+/-1%)
LatticeECP2 Family Data Sheet
Typical
100.5
12.11
3.30
2.05
1.25
0.80
1.65
196
100
10
93
Off-chip
Units
mA
Ω
Ω
Ω
Ω
Ω
V
V
V
V
V
On-chip
+
-