LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 6

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Slice
Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For
PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF.
Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they
enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such
as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro-
nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the
internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or
level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent
slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13
input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.
Figure 2-3. Slice Diagram
Slice 0
Slice 1
Slice 2
Slice 3
Slice
Routing
From
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Resources
FXB
FXA
CLK
LSR
2 LUT4s
M1
M0
CE
C1
D1
C0
D0
A1
B1
A0
B0
* Not in Slice 3
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
PFU BLock
Logic, Ripple, ROM
FCI To Different Slice/PFU
FCI From Different Slice/PFU
Logic, ROM
Modes
CARRY*
CARRY*
LUT4 &
LUT4 &
CO
CO
CI
CI
2-3
F/SUM
F/SUM
2 LUT4s and 2 Registers
Resources
LUT5
Mux
2 LUT4s
LatticeECP2 Family Data Sheet
PFF Block
SLICE
D
D
FF*
FF*
Logic, Ripple, ROM
Logic, Ripple, ROM
Logic, Ripple, ROM
Routing
Logic, ROM
OFX1
F1
Q1
To
OFX0
F0
Q0
Modes
Architecture