LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 10

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Table 2-4. GPLL and SPLL Blocks Signal Descriptions
Delay Locked Loops (DLL)
In addition to PLLs, the LatticeECP2 family of devices has two DLLs per device.
CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes
block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference
input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated
from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI
or from tapped signal from the Delay chain.
The PFD produces a binary number proportional to the phase and frequency difference between the reference and
feedback signals. This binary output of the PFD is feed into a Arithmetic Logic Unit (ALU). Based on these inputs,
the ALU determines the correct digital control codes to send to the delay chain in order to better match the refer-
ence and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL)
bus to its associated DLL_DEL delay block. The ALUHOLD input allows the user to suspend the ALU output at its
current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus.
The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the
outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output
to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45,
22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with
optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK out-
put signal is asserted when the DLL is locked. Figure 2-5 shows the DLL block diagram and Table 2-5 provides a
description of the DLL inputs and outputs.
The sysCLOCK DLL is configured at power-up and, if desired, can be reconfigured dynamically through the Serial
Memory Interface (SMI) bus. Users can drive the SMI interface from routing using Lattice software tools.
The user can configure the DLL for many common functions such as time reference delay mode and clock injection
removal mode. Lattice provides primitives in its design tools for these functions. For more information on the DLL,
please see details of additional technical documentation at the end of this data sheet.
CLKI
CLKFB
RST
RSTK
CLKOS
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
DPA MODES
DPHASE [3:0]
DDDUTY [3:0]
1. These signals are not available in SPLL.
Signal
1
1
1
1
I/O
—
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Clock input from external pin or routing
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
“1” to reset PLL counters, VCO, charge pumps and M-dividers
“1” to reset K-divider
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (no phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
Dynamic Delay Input
DPA (Dynamic Phase Adjust/Duty Cycle Select) mode
DPA Phase Adjust inputs
DPA Duty Cycle Select inputs
2-7
Description
LatticeECP2 Family Data Sheet
Architecture