LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 5

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
PFU Blocks
The core of the LatticeECP2 device consists of PFU blocks which are provided in two forms, the PFU and PFF. The
PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF
blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-
der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
Programmable
Function Units
(PFUs)
sysDSP Blocks
Multiply and
Accumulate Support
sysMEM Block RAM
18kbit Dual Port
Latch
FF/
LUT4 &
CARRY
D
Slice 0
Latch
FF/
LUT4 &
CARRY
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
CARRY
LUT4 &
D
Routing
Routing
From
2-2
To
Latch
FF/
LUT4 &
CARRY
D
Slice 2
Latch
FF/
CARRY
LUT4 &
D
LatticeECP2 Family Data Sheet
LUT4 &
CARRY
Slice 3
Flexible routing optimized
for speed, cost and routability
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
CARRY
LUT4 &
Architecture