LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 12

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
DLL_DEL Delay Block
Closely associated with each DLL is a DLL_DEL block. This is a delay block consisting of a delay line with taps and
a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKINDEL signal.
Typically this is the delay setting that the DLL uses to achieve phase alignment. This results in the delay providing a
calibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous
data. Note that it is possible to make small adjustments to the delay by programming registers available via the SMI
bus. The CLKINDEL signal feeds the edge clock network. Figure 2-6 shows the connections between the DLL
block and the DLL_DEL delay block. For more information, please see details of additional technical documentation
at the end of this data sheet.
Figure 2-6. DLL_DEL Delay Block
PLL/DLL Cascading
LatticeECP2 devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cascad-
ing. The allowable combinations are as follows:
• PLL to PLL supported
• PLL to DLL supported
The DLLs in the LatticeECP2 are used to shift the clock in relation to the data for source synchronous inputs. PLLs
are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL
blocks allows applications to utilize the unique benefits of both DLLs and PLLs.
For further information on the DLL, please see details of additional technical documentation at the end of this data
sheet.
Clock Dividers
LatticeECP2 devices have two clock dividers on the left and right sides of the device. These are intended to gener-
ate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or ÷8 mode and
maintains a known phase relationship between the divided down clock and the high-speed clock based on the
release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, DLL_DEL delay blocks,
routing or from an external clock input. The clock divider outputs serve as primary clock sources and feed into the
GDLLFB_PIO
CLKFB_CK
PLL_PIO
DLL_PIO
Routing
Routing
CLKOP
ECLK1
* Software selectable
*
*
*
CLKI
CLKFB
CLKI
DCNTL[8:0]
DLL_DEL Delay Block
2-9
DLL Block
LatticeECP2 Family Data Sheet
CLKOP
CLKOS
LOCK
CLKINDEL
Architecture