LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 16

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-10.
Figure 2-10. Edge Clock Sources
Primary Clock Routing
The clock routing structure in LatticeECP2 devices consists of a network of eight primary clock lines (CLK0 through
CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the
device. All the clock sources are connected to these muxes. Figure 2-11 shows the clock routing for one quadrant.
Each quadrant mux is identical. If desired, any clock can be routed globally
From Routing
From Routing
Sources for left edge clocks
Input
Input
DLL
PLL
Clock
Clock
Input
Input
DLL_DEL
GPLL
DLL
Routing
Routing
From
From
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
Clock Input
2-13
Clock Input
Clock Input
Routing
Routing
From
From
Sources for top
bottom edge
Sources for
edge clocks
LatticeECP2 Family Data Sheet
clocks
Sources for right edge clocks
GPLL
DLL
DLL_DEL
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
DLL
PLL