LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 20

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-17. Edge Clock Mux Connections
sysMEM Memory
LatticeECP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-Kbit
RAM with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by imple-
menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for
each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.
GPLL Output CLKOP
GPLL Output CLKOS
DLL Output CLKOP
DLL Output CLKOS
GPLL Input Pad
GPLL Input Pad
Clock Input Pad
CLKINDEL
CLKINDEL
Input Pad
Input Pad
Routing
Routing
Routing
2-17
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
Edge Clocks
Edge Clocks
Edge Clocks
(Both Mux)
ECLK1
ECLK2
LatticeECP2 Family Data Sheet
Architecture