LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 45

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Configuration and Testing
This section describes the configuration and testing features of the LatticeECP2 family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test
Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
V
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeECP2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG port, support both byte-wide and serial configuration.
The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-
System Configuration specification. The sysCONFIG port is a 20-pin interface with six I/Os used as dedicated pins
with the remainder used as dual-use pins. See Lattice technical note number TN1108, LatticeECP2 sysCONFIG
Usage Guide for more information on using the dual-use pins as general purpose I/Os.
There are five ways to configure a LatticeECP2 device:
1. Industry standard SPI serial memories
2. Industry standard byte wide flash with an ispMACH™ 4000, providing control and addressing
3. System microprocessor to drive a sysCONFIG port or JTAG TAP
4. Industry standard FPGA boot PROM memory
5. JTAG
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration
port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any
time after power-up by sending the appropriate command through the TAP port.
Enhanced Configuration Option
LatticeECP2 devices have enhanced configuration features such as: decryption support, TransFR™ I/O and dual
boot image support.
1. Decryption Support
2. TransFR (Transparent Field Reconfiguration)
CCJ
LatticeECP2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES
encrypted bitstream, securing designs and deterring design piracy. The decryption block supports nearly all the
programming modes.
TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without
interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur-
ing device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. See Lattice technical note number TN1087, Minimizing System Interruption During Configuration
Using TransFR Technology, for details.
and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
2-42
LatticeECP2 Family Data Sheet
Architecture