ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 80

• Manufacturer Part Number: ATMEGA16-16AU SL602
• Manufacturer: Atmel

2466T–AVR–07/10
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of Period 2 in
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without Compare Match:
•
•
OCR0A changes its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must be correspond to the result of an
up-counting Compare Match.
The Timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
Figure 33
f
OCnPCPWM
OCn has a transition from high to low even though there
Figure
=
----------------- -
N 510
f
clk_I/O
⋅
33. When the OCR0A value is MAX the
ATmega16(L)
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