ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 223
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ATMEGA16-16AU SL602
Manufacturer Part Number
ATMEGA16-16AU SL602
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA16-16AU_SL602.pdf
(357 pages)
- Current page: 223 of 357
- Download datasheet (8Mb)
2466T–AVR–07/10
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the
TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP
input signals are internally pulled high and the JTAG is enabled for Boundary-scan and program-
ming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP
controller is not shifting data, and must therefore be connected to a pull-up resistor or other
hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The
device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
Figure 112. Block Diagram
TDI
TDO
TCK
TMS
CONTROLLER
M
U
X
TAP
DEVICE BOUNDARY
INSTRUCTION
BREAKPOINT
SCAN CHAIN
REGISTER
REGISTER
REGISTER
BYPASS
ID
ADDRESS
DECODER
JTAG PROGRAMMING
MEMORY
FLASH
AND CONTROL
BREAKPOINT
OCD STATUS
INTERFACE
UNIT
Address
Data
I/O PORT 0
I/O PORT n
INTERNAL
FLOW CONTROL
CHAIN
SCAN
UNIT
BOUNDARY SCAN CHAIN
COMMUNICATION
JTAG / AVR CORE
PC
Instruction
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
ATmega16(L)
223
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