ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 141

• Manufacturer Part Number: ATMEGA16-16AU SL602
• Manufacturer: Atmel

2466T–AVR–07/10
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
rized below:
Table 56. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
tionality is summarized below:
Table 57. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 58. Relationship Between SCK and the Oscillator Frequency
SPI2X
CPOL
CPHA
0
0
0
0
1
1
1
1
0
1
0
1
Figure 67
SPR1
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
and
Sample
Falling
Rising
Setup
Figure 68
Figure 67
SPR0
0
1
0
1
0
1
0
1
for an example. The CPOL functionality is summa-
and
Figure 68
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
for an example. The CPHA func-
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
ATmega16(L)
osc
141
is