ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 71
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ATMEGA16-16AU SL602
Manufacturer Part Number
ATMEGA16-16AU SL602
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA16-16AU_SL602.pdf
(357 pages)
- Current page: 71 of 357
- Download datasheet (8Mb)
8-bit
Timer/Counter0
with PWM
Overview
Registers
2466T–AVR–07/10
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The
main features are:
•
•
•
•
•
•
•
A simplified block diagram of the 8-bit Timer/Counter is shown in
ment of I/O pins, refer to
I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are
listed in the
Figure 27. 8-bit Timer/Counter Block Diagram
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC0).
Single Compare Unit Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
External Event Counter
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)
“8-bit Timer/Counter Register Description” on page
Timer/Counter
TCNTn
OCRn
=
“Pinout ATmega16” on page
direction
BOTTOM
count
clear
= 0
Control Logic
=
TCCRn
TOP
0xFF
2. CPU accessible I/O Registers, including
clk
Tn
Generation
Waveform
83.
Figure
Clock Select
( From Prescaler )
Detector
Edge
ATmega16(L)
27. For the actual place-
See “Output Compare
OCn
(Int.Req.)
TOVn
(Int.Req.)
OCn
T0
Tn
).
71
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