ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 166

• Manufacturer Part Number: ATMEGA16-16AU SL602
• Manufacturer: Atmel

USART Control and
Status Register C –
UCSRC
2466T–AVR–07/10
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
The UCSRC Register shares the same I/O location as the UBRRH Register. See the
UBRRH/ UCSRC Registers” on page 162
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when
reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 63. UMSEL Bit Settings
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the PE Flag in UCSRA will be set.
Table 64. UPM Bits Settings
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 65. USBS Bit Settings
Bit
Read/Write
Initial Value
UPM1
UMSEL
0
0
1
1
0
1
URSEL
USBS
R/W
7
1
0
1
UMSEL
R/W
6
0
UPM0
Mode
Asynchronous Operation
Synchronous Operation
0
1
0
1
UPM1
R/W
5
0
UPM0
R/W
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
4
0
section which describes how to access this register.
USBS
R/W
3
0
UCSZ1
Stop Bit(s)
R/W
2
1
1-bit
2-bit
UCSZ0
R/W
1
1
ATmega16(L)
UCPOL
R/W
0
0
UCSRC
“Accessing
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