ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 115
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ATMEGA16-16AU SL602
Manufacturer Part Number
ATMEGA16-16AU SL602
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA16-16AU_SL602.pdf
(357 pages)
- Current page: 115 of 357
- Download datasheet (8Mb)
Timer/Counter
Interrupt Mask
Register – TIMSK
Timer/Counter
Interrupt Flag Register
– TIFR
2466T–AVR–07/10
(1)
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
Note:
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in
this section. The remaining bits are described in their respective timer sections.
See “Accessing 16-bit Registers” on page 92.
described in this section. The remaining bits are described in their respective timer sections.
OCIE2
OCF2
R/W
R/W
7
0
7
0
(See “Interrupts” on page
(See “Interrupts” on page
TOIE2
TOV2
R/W
R/W
6
0
6
0
45.) is executed when the TOV1 Flag, located in TIFR, is set.
TICIE1
ICF1
R/W
R/W
5
0
5
0
45.) is executed when the ICF1 Flag, located in TIFR, is set.
OCIE1A
OCF1A
R/W
R/W
4
0
4
0
45.) is executed when the OCF1A Flag, located in
45.) is executed when the OCF1B Flag, located in
OCIE1B
OCF1B
R/W
R/W
3
0
3
0
TOV1
TOIE1
R/W
R/W
2
0
2
0
OCIE0
OCF0
R/W
R/W
1
0
1
0
ATmega16(L)
TOV0
TOIE0
R/W
R/W
0
0
0
0
TIMSK
TIFR
115
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