ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 209

• Manufacturer Part Number: ATMEGA16-16AU SL602
• Manufacturer: Atmel

Differential Gain
Channels
2466T–AVR–07/10
Figure 103. ADC Timing Diagram, Auto Triggered Conversion
Figure 104. ADC Timing Diagram, Free Running Conversion
Table 81. ADC Conversion Time
When using differential gain channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
2
Conversion
Complete
3
One Conversion
Sample & Hold
11
4
Sample & Hold (Cycles
12
5
from Start of
Conversion)
6
1.5/2.5
13
13.5
1.5
2
7
One Conversion
ADC2
Next Conversion
1
MSB of Result
LSB of Result
8
. A conversion initiated by the user (that is,
2
MUX and REFS
Update
9
Conversion
10
3
Complete
Conversion Time (Cycles)
11
Sample & Hold
4
12
ADC2
ATmega16(L)
13/14
13
13.5
25
13
equal to half the ADC
MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
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