ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 108

• Manufacturer Part Number: ATMEGA16-16AU SL602
• Manufacturer: Atmel

Timer/Counter
Timing Diagrams
2466T–AVR–07/10
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle
with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, No Prescaling
Figure 50
Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 51
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams
TCNTn
OCRnx
OCFnx
TCNTn
OCRnx
(clk
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
shows the same timing data, but with the prescaler enabled.
/8)
/1)
shows the count sequence close to TOP in various modes. When using phase and
OCRnx - 1
OCRnx - 1
Figure 49
OCRnx
OCRnx
shows a timing diagram for the setting of OCF1x.
OCRnx Value
OCRnx Value
OCRnx + 1
OCRnx + 1
T1
ATmega16(L)
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
/8)
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